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ds04-21355-1e fujitsu semiconductor data sheet assp single serial input pll frequency synthesizer on-chip 2.5 ghz prescaler MB15E07L n description the fujitsu MB15E07L is serial input phase locked loop (pll) frequency synthesizer with a 2.5 ghz prescaler. a 32/33 or a 64/65 can be selected for the prescaler that enables pulse swallow operation. the latest bicmos process technology is used, resuitantly a supply current is limited as low as 4.5 ma typ. this operates with a supply voltage of 3.0 v (typ.) furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. as a result of this, MB15E07L is ideally suitable for digital mobile communications, such as gsm (global system for mobile communications). n features high frequency operation: 2.5 ghz max. (@ p = 64/65) 2.0 ghz max. (@ p = 32/33) low power supply voltage: v cc = 2.7 to 3.6 v very low power supply current: i cc = 4.5 ma typ. (v cc = 3 v) power saving function: i ps = 0.1 m a typ. (v cc = 3 v) pulse swallow function: 32/33 or 64/65 serial input 14-bit programmable reference divider: r = 5 to 16,383 serial input 18-bit programmable divider consisting of: - binary 7-bit swallow counter: 0 to 127 - binary 11-bit programmable counter: 5 to 2,047 wide operating temperature: ta = ?0 to +85 c plastic 16-pin ssop package (fpt-16p-m05) and 16-pads bcc package (lcc-16p-m02) n packages 16-pin, plastic ssop 16-pads, plastic bcc (fpt-16p-m05) (lcc-16p-m02) to top / lineup / index
2 MB15E07L n pin assignments clock (fpt-16p-m05) to p 1 2 3 4 5 6 16 15 14 13 12 11 7 8 10 9 view osc in f r v p v cc osc out d o f p ld/fout zc ps xfin fin le data ssop-16 pin to p view v p v cc osc out d o f p ld/fout zc ps xfin le data gnd (lcc-16p-m02) gnd 1 2 3 4 5 6 78 9 10 11 12 13 14 16 15 bcc-16 pads fin clock osc in f r to top / lineup / index
3 MB15E07L n pin descriptions pin no. pin name i/o descriptions ssop-16 bcc-16 1 16 osc in i programmable reference divider input. oscillator input. connection for an crystal or a tcxo. tcxo should be connected with a coupling capacitor. 2 1 osc out o oscillator output. connection for an external crystal. 32v p power supply voltage input for the charge pump. 43v cc power supply voltage input. 54d o o charge pump output. phase of the charge pump can be reversed by fc bit. 6 5 gnd ground. 7 6 xfin i prescaler complementary input, and should be grounded via a capacitor. 8 7 fin i prescaler input. connection with an external vco should be done with ac coupling. 9 8 clock i clock input for the 19-bit shift register. data is shifted into the shift register on the rising edge of the clock. (open is prohibited.) 10 9 data i serial data input using binary code. the last bit of the data is a control bit. (open is prohibited.) control bit = ? ; data is transmitted to the programmable reference counter. control bit = ? ; data is transmitted to the programmable counter. 11 10 le i load enable signal input (open is prohibited.) when le is high, the data in the shift register is transferred to a latch, according to the control bit in the serial data. 12 11 ps i power saving mode control. this pin must be set at ? at power-on. (open is prohibited.) ps = ? ; normal mode ps = ? ; power saving mode 13 12 zc i forced high-impedance control for the charge pump (with internal pull up resistor.) zc = ? ; normal d o output. zc = ? ; d o becomes high impedance. 14 13 ld/fout o lock detect signal output (ld)/phase comparator monitoring output (fout). the output signal is selected by lds bit in the serial data. lds = ? ; outputs fout (f r /f p monitoring output) lds = ? ; outputs ld (? at locking, ? at unlocking.) 15 14 f po phase comparator output for an external charge pump. nch open drain output. 16 15 f ro phase comparator output for an external charge pump. cmos output. to top / lineup / index
4 MB15E07L n block diagram osc in osc out v p v cc crystal oscillator circuit 17-bit latch programmable reference divider binary 14-bit reference counter phase comparator super charger ld/fout data 19-bit shift register 19-bit shift register 7-bit latch 18-bit latch 11-bit latch binary 7-bit swallow counter programmable divider binary 11-bit programmable counter d o gnd xfin clock le ps f p f r prescaler 32/33, 64/65 le sw md f p f p f p f r f r ld/f r /f p selector intermittent mode control (power save) le fin ld lock detector sw c n t 1-bit control latch 14-bit latch 3-bit latch lds fc zc control circuit note: ssop-16 pin 1 2 12 16 11 10 9 7 8 6 4 14 13 3 5 15 to top / lineup / index
5 MB15E07L n absolute maximum ratings warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions warning: recommended operating conditions are normal operating ranges for the semiconductor device. all the devices electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representative beforehand. handiing precautions this device should be transported and stores in anti-static containers. this is a static-sensitive device; take proper anti-esd precautions. ensure that personnel and equipment are properly grounded. cover workbenches with grounded conductive mats. always turn the power supply off before inserting or removing the device from its socket. protect leads with a conductive sheet when handling or transporting pc boards with devices. parameter symbol rating unit remark min. max. power supply voltage v cc ?.5 +4.0 v v p v cc +6.0 v input voltage v i ?.5 v cc +0.5 v output voltage v o ?.5 v cc +0.5 v output current i o ?0 +10 ma except d o output i do ?5 +25 ma d o output storage temperature t stg ?5 +125 c parameter symbol value unit remark min. typ. max. power supply voltage v cc 2.7 3.0 3.6 v v p v cc 6.0 v input voltage v i gnd v cc v operating temperature ta ?0 +85 c to top / lineup / index
6 MB15E07L n electrical characteristics (v cc = 2.7 to 3.6 v, ta = ?0 to +85 c) *1: conditions; v cc = 3.0 v, ta = +25 c, in locking state. *2: v cc = 3.0 v, fosc = 12.8 mhz, ta = +25 c, in power saving mode. *3: ac coupling with a 1000 pf capacitor connected. *4: the symbol (minus) means direction of current ?w. *5: ta = +25 c parameter symbol condition value unit min. typ. max. power supply current* 1 i cc *1 ? = 2500 mhz, fosc = 12 mhz, p = 64/65 4.5 ma power saving current ips *2 zc = ? or open 10 m a operating frequency fin p = 32/33 100 2000 mhz p = 64/65 100 2500 crystal oscillator operating fre- quency f osc min. 500 mv p-p 3 40 mhz input sensitivity ? *3 vfin 50 w system (refer to the test circuit.) ?0 +2 dbm osc in *3 v osc 0.5 v cc v p-p input voltage data, clock, le, ps, zc v ih ? cc 0.7 v v il v cc 0.3 input current data, clock, le, ps i ih *4 ?.0 +1.0 m a i il *4 ?.0 +1.0 zc i ih *4 ?.0 +1.0 m a i il *4 pull up input ?00 0 osc in i ih 0 +100 m a i il *4 ?00 0 output voltage f pv ol open drain output 0.4 v f r, ld/fout v oh v cc = 3 v, i oh = ? ma v cc ?0.4 v v ol v cc = 3 v, i ol = 1 ma 0.4 d o v doh v cc = 3 v, i oh = ? ma v p ?0.4 v v dol v cc = 3 v, i ol = 1 ma 0.4 high impedance cutoff current d o i off v cc = 3 v, v p = 6 v v oop = gnd to 6 v 3.0 na output current f pi ol open drain output 1.0 ma f r, ld/fout i oh *4 ?.0 ma i ol 1.0 d o i doh *4, 5 v cc = 3 v, v p = 3 v, v doh = 2.0 v, ta = +25 c ?1 6 ma i dol *4 v cc = 3 v, v p = 3 v v dol = 1.0 v, ta = +25 c 815 to top / lineup / index
7 MB15E07L n function descriptions 1. pulse swallow function the divide ratio can be calculated using the following equation: f vco = [(m n) + a] f osc ? r (a < n) f vco : output frequency of external voltage controlled oscillator (vco) n : preset divide ratio of binary 11-bit programmable counter (5 to 2,047) a : preset divide ratio of binary 7-bit swallow counter (0 a 127) f osc : output frequency of the reference frequency oscillator r : preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383) m : preset divide ratio of modules prescaler (32 or 64) 2. serial data input serial data is processed using the data, clock, and le pins. serial data controls the programmable reference divider and the programmable divider separately. binary serial data is entered through the data pin. one bit of data is shifted into the shift register on the rising edge of the clock. when the load enable pin is high, stored data is latched according to the control bit data as follows: table.1 control bit (1) shift register con?uration control bit (cnt) destination of serial data h 17 bit latch (for the programmable reference divider) l 18 bit latch (for the programmable divider) programmable reference counter c n t 1 2 r 2 3 r 4 4 r 5 5 r 6 6 r 7 7 r 8 8 r 9 9 r 10 10 r 11 11 r 12 12 r 13 13 r 14 14 sw 15 fc 16 lds 17 lsb msb data flow r 1 r 3 18 cnt : control bit [table. 1] r1 to r14 : divide ratio setting bit for the programmable reference counter (5 to 16,383) [table. 2] sw : divide ratio setting bit for the prescaler (32/33 or 64/65) [table. 5] fc : phase control bit for the phase comparator [table. 7] lds : ld/fout signal select bit [table. 6] note : start data input with msb ?st to top / lineup / index
8 MB15E07L table.2 binary 14-bit programmable reference counter data setting note: divide ratio less than 5 is prohibited. table.3 binary 11-bit programmable counter data setting note: divide ratio less than 5 is prohibited. divide ratio (r) r 14 r 13 r 12 r 11 r 10 r 9 r 8 r 7 r 6 r 5 r 4 r 3 r 2 r 1 5 00000000000101 6 00000000000110 16383 11111111111111 divide ratio (n) n 11 n 10 n 9 n 8 n 7 n 6 n 5 n 4 n 3 n 2 n 1 5 00000000101 6 00000000110 2047 1 1 111111111 programmable reference counter lsb msb data flow cnt : control bit [table. 1] n1 to n11 : divide ratio setting bits for the programmable counter (5 to 2,047) [table. 3] a1 to a7 : divide ratio setting bits for the swallow counter (0 to 127) [table. 4] note : start data input with msb ?st c n t 1 2 3 45 a 1 6 a 2 7 a 3 8 a 4 9 a 5 10 a 6 11 a 7 12 n 1 13 n 2 14 n 3 15 n 4 16 n 5 17 n 6 18 n 7 19 n 8 n 9 n 10 n 11 to top / lineup / index
9 MB15E07L table.4 binary 7-bit swallow counter data setting table.5 prescaler data setting table.6 ld/fout output select data setting (2) relation between the fc input and phase characteristics the fc bit changes the phase characteristics of the phase comparator. both the internal charge pump output level (d o ) and the phase comparator output ( f r, f p) are reversed according to the fc bit. also, the monitor pin (fout) output is controlled by the fc bit. the relationship between the fc bit and each of d o , f r, and f p is shown below. table.7 fc bit data setting (lds = ?? * : high impedance divide ratio (a) a 7 a 6 a 5 a 4 a 3 a 2 a 1 0 0000000 1 0000001 127 1 1 1 1 1 1 1 sw prescaler divide ratio h 32/33 l 64/65 lds ld/fout output signal h fout signal l ld signal fc = high fc = low d o f r f p ld/fout d o f r f p ld/fout f r > f p h l l fout = f r lhz* fout = f p f r < f p lhz* hll f r = f p z*lz* z*lz* to top / lineup / index
10 MB15E07L when designing a synthesizer, the fc pin setting depends on the vco and lpf characteristics. table.8 ps pin setting table.9 zc pin setting ps pin status h normal mode l power saving mode zc pin d o output h normal output l high impedance * : when the lpf and vco characteristics are similar to (1), set fc bit high. * : when the vco characteristics are similar to (2), set fc bit low. lpf input voltage vco output frequency pll lpf vco (1) (2) to top / lineup / index
11 MB15E07L 3. power saving mode (intermittent mode control circuit) setting a ps pin to low, the ic enters into power saving mode resultatly current consumption can be limited to 10 m a (max.). setting ps pin to high, power saving mode is released so that the ic works normally. in addition, the intermittent operation control circuit is included which helps smooth start up from the power saving mode. in general, the power consumption can be saved by the intermittent operation that powering down or waking up the synthesizer. such case, if the pll is powered up uncontrolled, the resulting phase comparator output signal is unpredictable due to an unde?ed phase relation between reference frequency (f r ) and comparison frequency (f p ) and may in the worst case take longer time for lock up of the loop. to prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector during power up, thus keeping the loop locked. during the power saving mode, the corresponding section except for indispensable circuit for the power saving function stops working, then current consumption is reduced to 10 m a (max.). note: while the power saving mode is executed, zc pin should be set at ? or open. if zc is set at ? during power saving mode, approximately 10 m a current ?ws. ps pin must be set ? at power-on. the power saving mode can be released (ps : l ? h) 1 m s later after power supply remains stable. during the power saving mode, it is possible to input the serial data. on v cc clock data le ps (1) (2) (3) (1) ps = l (power saving mode) at power-on (2) set serial data after power supply remains stable. (3) relase power saving mode (ps : l ? h) after setting serial data. to top / lineup / index
12 MB15E07L 4. serial data input timing on rising edge of the clock, one bit of the data is transferred into the shift register. parameter unit max. typ. min. t 1 t 2 t 3 t 4 ns ns ns ns 20 20 30 30 100 20 100 t 5 t 6 t 7 ns ns ns parameter unit max. typ. min. msb data clock le ~ ~ lsb ~ ~ t 4 t 5 t 6 t 2 t 1 t 7 control bit invalid data 2nd. data 1st. data t 3 to top / lineup / index
13 MB15E07L n phase comparator output waveform notes: 1. phase error detection range: ? p to +2 p 2. pulses on d o output signal during locked state are output to prevent dead zone. 3. ld output becomes low when phase is t wu or more. ld output becomes high when phase error is t wl or less and continues to be so for three cycles or more. 4. t wu and t wl depend on osc in input frequency. t wu > 4/fosc (e. g. t wu > 312.5 ns, foscin = 12.8 mhz) t wl < 8/fosc (e. g. t wl < 625.0 ns, foscin = 12.8 mhz) 5. ld becomes high during the power saving mode (ps = ??) f p f r ld [ fc = ??] f p f r d o [ fc = ??] f p f r d o h l z t wu t wl h l z to top / lineup / index
14 MB15E07L n typical characteristics 1. ? input sensitivity +10 0 e10 e20 e30 e40 input frequency vs. input sensitivity (prescaler = 64/65) input frequency (fin) 0 1000 2000 input sensitivity (v fin) 3000 (mhz) (dbm) v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = +25 c spec +10 0 e10 e20 e30 e40 input frequency vs. input sensitivity (prescaler = 32/33) input frequency (fin) 0 1000 2000 input sensitivity (v fin) 3000 (mhz) (dbm) v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v ta = +25 c spec to top / lineup / index
15 MB15E07L 2. osc in input sensitivity +10 ?0 ?0 ?0 ?0 0 input frequency vs. input sensitivity input frequency (fosc) 0 50 100 150 (mhz) input sensitivity (v osc ) (dbm) ta = +25 c v cc = 2.7 v v cc = 3.0 v v cc = 3.6 v spec to top / lineup / index
16 MB15E07L 3. d o output current i oh vs. v oh v oh (ma) .0000 ido 2.500/div ?5.00 (v) 5.000 .5000 /div .0000 i oh ta = +25 c v cc = 3.0 v v p = 3.0 v, 5.0 v i ol vs. v ol v ol (ma) .0000 ido 2.500/div e25.00 (v) 5.000 .5000 /div .0000 i ol ta = +25 c v cc = 3.0 v v p = 3.0 v, 5.0 v to top / lineup / index
17 MB15E07L 4. ? input impedance 5. osc in input impedance 10.715 w e50.275 w 1 ghz 11.118 w e10.846 w 1.5 ghz 16.718 w 20.081 w 2 ghz 1; 2; 3; 4; 43.439 w 38.307 w 2.5 ghz 1 4 3 2 4.656 k w e19.064 k w 3 mhz 704.75 w e5.3735 k w 10 mhz 388.25 w e2.775 k w 20 mhz 1; 2; 3; 4; 136.38 w e1.5275 k w 40 mhz 4 1 2 3 to top / lineup / index
18 MB15E07L n test circuit (for measuring input sensitivity fin/osc in ) 1000 pf 50 w 0.1 m f v cc v p s ?g s ?g 0.1 m f 1000 pf 50 w controller (setting divide ratio) oscilloscope 1000 pf v cc 87654321 9 1213141516 10 11 note: ssop-16 pin to top / lineup / index
19 MB15E07L n application example 1000 pf 0.1 m f c 1 x?tal lpf vco osc in osc out v p v cc d o gnd xfin fin c 2 output from a controller c 1 , c 2 : depend on the crystal parameters v p : 6v max. 12 k w 12 k w 10 k w 10 k w 0.1 m f 1000 pf lock detect. f r f p ld/fout zc ps le data clock v p 16 15 14 13 12 11 10 9 1 234 5678 MB15E07L note: ssop-16 pin to top / lineup / index
20 MB15E07L n ordering information part number package remarks MB15E07Lpfv1 16-pin, plastic ssop (fpt-16p-m05) MB15E07Lpv 16-pads, plastic bcc (lcc-16p-m02) to top / lineup / index
21 MB15E07L n package dimensions (continued) +0.20 C0.10 +.008 C.004 +0.10 C0.05 +.004 C.002 +0.05 C0.02 +.002 C.001 index "a" 0.10(.004) 1.25 .049 0.22 .009 0.15 .006 (.0256.0047) * (.173.004) (.252.008) nom 6.400.20 4.400.10 5.40(.213) 0.650.12 * 5.000.10(.197.004) 4.55(.179)ref details of "a" part 0 10 (stand off) 0.100.10(.004.004) (.020.008) 0.500.20 1994 fujitsu limited f16013s-2c-4 c dimensions in mm (inches ) (mounting height) 16-pin, plastic ssop (fpt-16p-m05) * : these dimensions do not include resin protrusion. to top / lineup / index
22 MB15E07L (continued) c 1996 fujitsu limited c16013s-1c-1 0.3250.10 (.013.004) 0.65(.026)typ 3.40(.134)typ 1.725(.068) typ 1.15(.045)typ "b" "a" 0.400.10 (.016.004) 2.45(.096) 0.80(.032) typ typ 3.400.10 (.1339.0039) 4.550.10 (.179.004) 0.80(.032)max 0.0850.04 (.003.002) (stand off) 0.40(.016) 45? e-mark 0.05(.002) 6 9 1 14 9 14 1 6 0.600.10 (.024.004) 0.600.10 (.024.004) details of "b" part 0.400.10 (.016.004) 0.750.10 (.030.004) details of "a" part dimensions in mm (inches ) (mouting height) * : these dimensions do not include resin protrusion. 16-pins, plastic bcc (lcc-16p-m02) to top / lineup / index
23 MB15E07L all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan. fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 922-9179 customer response center mon. ?fri.: 7 am ?5 pm (pst) tel: (800) 866-8608 fax: (408) 922-9179 http://www.fujitsumicro.com/ europe fujitsu mikroelektronik gmbh am siebenstein 6-10 d-63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 http:.//www.fujitsu-ede.com/ asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281 0770 fax: (65) 281 0220 http://www.fmap.com.sg/ f9710 ? fujitsu limited printed in japan to top / lineup / index

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